Microchip Icicle Kit BSP update

- Kernel upadated to 6.1.43
- Uboot updated to 2023.07.02

Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>

microchip/common/bsp/linux-icicle-kit.nix

@@ -3,7 +3,7 @@
 with pkgs;
 
 buildLinux (args // rec {
-  version = "5.15.92-linux4microchip+fpga-2023.02";
+  version = "6.1.43-linux4microchip+fpga-2023.09";
 
   # modDirVersion needs to be x.y.z, will automatically add .0 if needed
   modDirVersion = version;
@@ -63,7 +63,7 @@ buildLinux (args // rec {
   src = fetchFromGitHub {
     owner = "linux4microchip";
     repo = "linux";
-    rev = "360a547daec2a69169be49d3da9cca8b1ecb325f";
-    sha256 = "sha256-ri2d91bHmcFkV2PjwRNho1XQixKttJKoG/qiOdeB01M=";
+    rev = "25e35c7c54ad853d03c14a02b189b408cb5b5eb3";
+    sha256 = "sha256-wj7lz247MkhxmhSHUcNeWmcZK+DL+5PAnLwTmALD97M=";
   };
 } // (args.argsOverride or { }))

microchip/common/bsp/patches/0001-Boot-environment-for-Microchip-Iciclle-Kit.patch

@@ -1,26 +1,27 @@
-From 2085960b5dfc7058d572cfb90fa349efe9bacdf2 Mon Sep 17 00:00:00 2001
-From: Ganga Ram <ganga.jaiswal@gmail.com>
-Date: Mon, 24 Apr 2023 10:15:22 +0400
+From 313309c07e904ba48386568c361f4a3265829a81 Mon Sep 17 00:00:00 2001
+From: Ganga Ram <Ganga.Ram@tii.ae>
+Date: Tue, 10 Oct 2023 17:07:49 +0400
 Subject: [PATCH] Boot environment for Microchip Iciclle Kit
 
-Signed-off-by: Ganga Ram <ganga.jaiswal@gmail.com>
+Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
 ---
  include/configs/microchip_mpfs_icicle.h | 3 +++
  1 file changed, 3 insertions(+)
 
 diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
-index 9ef5425c9f..c8a1f7c9df 100644
+index 0b9eb59bc4..59b4465f1e 100644
 --- a/include/configs/microchip_mpfs_icicle.h
 +++ b/include/configs/microchip_mpfs_icicle.h
-@@ -71,6 +71,9 @@
- #define CONFIG_EXTRA_ENV_SETTINGS \
-	"bootm_size=0x10000000\0" \
-	"scriptaddr=0x8e000000\0" \
+@@ -125,6 +125,9 @@
+ #define CFG_EXTRA_ENV_SETTINGS \
+ 	"bootm_size=0x10000000\0" \
+ 	"scriptaddr=0x8e000000\0" \
 +  "kernel_addr_r=0x8e000000\0" \
 +  "ramdisk_addr_r=0x90000000\0" \
 +  "fdt_addr_r=0x92000000\0" \
-	BOOTENV_DESIGN_OVERLAYS \
-	BOOTENV \
-
---
+ 	BOOTENV_DESIGN_OVERLAYS \
+ 	BOOTENV \
+ 
+-- 
 2.39.2
+

microchip/common/bsp/patches/0002-Riscv-Fix-build-against-binutils-2.38.patch

@@ -1,51 +0,0 @@
-From 8afd811876b1ce8d6da6d5c804452a2b15805f5a Mon Sep 17 00:00:00 2001
-From: Ganga Ram <Ganga.Ram@tii.ae>
-Date: Wed, 5 Jul 2023 11:32:44 +0400
-Subject: [PATCH] From: Ganga Ram <Ganga.Ram@tii.ae> Date: Wed, 05 July 2023
- 06:15:22 +0400 Subject: [PATCH] Riscv-Fix-build-against-binutils-2.38
-
-The following description is copied from the equivalent patch for the
-Linux Kernel proposed by Aurelien Jarno:
-
-From version 2.38, binutils default to ISA spec version 20191213. This
-means that the csr read/write (csrr*/csrw*) instructions and fence.i
-instruction has separated from the `I` extension, become two standalone
-extensions: Zicsr and Zifencei. As the kernel uses those instruction,
-this causes the following build failure:
-
-arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i', extension `zifencei' required
-arch/riscv/cpu/cpu.c:94: Error: unrecognized opcode `csrs sstatus,a5', extension `zicsr' required
-arch/riscv/cpu/cpu.c:95: Error: unrecognized opcode `csrw 0x003,0', extension `zicsr' required
-
-More detail: https://patchwork.ozlabs.org/series/283391/mbox/
-
-Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
----
- arch/riscv/Makefile | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
-index 0b80eb8d86..53d1194ffb 100644
---- a/arch/riscv/Makefile
-+++ b/arch/riscv/Makefile
-@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
- 	CMODEL = medany
- endif
- 
--ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
-+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
-+
-+# Newer binutils versions default to ISA spec version 20191213 which moves some
-+# instructions from the I extension to the Zicsr and Zifencei extensions.
-+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
-+ifeq ($(toolchain-need-zicsr-zifencei),y)
-+	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
-+endif
-+
-+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
- 	     -mcmodel=$(CMODEL)
- 
- PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
--- 
-2.39.2
-

microchip/common/bsp/uboot.nix

@@ -8,14 +8,14 @@ with pkgs; let
 in
 buildUBoot rec {
   pname = "uboot";
-  version = "linux4microchip+fpga-2023.06";
+  version = "linux4microchip+fpga-2023.09";
 
   src = fetchFromGitHub {
     owner = "polarfire-soc";
     repo = "u-boot";
     # from mpfs-uboot-2022.01 branch
-    rev = "7e19f9dff788025403ac6a34d9acf8736eef32ff";
-    sha256 = "sha256-1qmifjjNxPOUWRgZdQk6Ld5KGQk/PypSRK/ILPSsTLs";
+    rev = "8f5e331e3f09cdf469d528905f5d6a7139016634";
+    sha256 = "sha256-UElnkRgzcvTjAo5X9N8c1fCTrTxdpAGkntcpQlqgDy8=";
   };
 
   extraMakeFlags = [
@@ -24,7 +24,6 @@ buildUBoot rec {
 
   patches = [
     ./patches/0001-Boot-environment-for-Microchip-Iciclle-Kit.patch
-    ./patches/0002-Riscv-Fix-build-against-binutils-2.38.patch
   ];
   defconfig = "${targetBoard}_defconfig";
   enableParallelBuilding = true;