Microchip Icicle Kit BSP update
- Kernel upadated to 6.1.43 - Uboot updated to 2023.07.02 Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
This commit is contained in:
Ganga Ram
mergify[bot]
parent
d6b554a85c
commit
3d4a18fac8
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@ -3,7 +3,7 @@
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with pkgs;
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buildLinux (args // rec {
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version = "5.15.92-linux4microchip+fpga-2023.02";
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version = "6.1.43-linux4microchip+fpga-2023.09";
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# modDirVersion needs to be x.y.z, will automatically add .0 if needed
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modDirVersion = version;
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@ -63,7 +63,7 @@ buildLinux (args // rec {
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src = fetchFromGitHub {
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owner = "linux4microchip";
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repo = "linux";
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rev = "360a547daec2a69169be49d3da9cca8b1ecb325f";
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sha256 = "sha256-ri2d91bHmcFkV2PjwRNho1XQixKttJKoG/qiOdeB01M=";
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rev = "25e35c7c54ad853d03c14a02b189b408cb5b5eb3";
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sha256 = "sha256-wj7lz247MkhxmhSHUcNeWmcZK+DL+5PAnLwTmALD97M=";
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};
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} // (args.argsOverride or { }))
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@ -1,26 +1,27 @@
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From 2085960b5dfc7058d572cfb90fa349efe9bacdf2 Mon Sep 17 00:00:00 2001
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From: Ganga Ram <ganga.jaiswal@gmail.com>
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Date: Mon, 24 Apr 2023 10:15:22 +0400
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From 313309c07e904ba48386568c361f4a3265829a81 Mon Sep 17 00:00:00 2001
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From: Ganga Ram <Ganga.Ram@tii.ae>
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Date: Tue, 10 Oct 2023 17:07:49 +0400
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Subject: [PATCH] Boot environment for Microchip Iciclle Kit
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Signed-off-by: Ganga Ram <ganga.jaiswal@gmail.com>
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Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
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---
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include/configs/microchip_mpfs_icicle.h | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
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index 9ef5425c9f..c8a1f7c9df 100644
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index 0b9eb59bc4..59b4465f1e 100644
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--- a/include/configs/microchip_mpfs_icicle.h
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+++ b/include/configs/microchip_mpfs_icicle.h
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@@ -71,6 +71,9 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"scriptaddr=0x8e000000\0" \
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@@ -125,6 +125,9 @@
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#define CFG_EXTRA_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"scriptaddr=0x8e000000\0" \
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+ "kernel_addr_r=0x8e000000\0" \
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+ "ramdisk_addr_r=0x90000000\0" \
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+ "fdt_addr_r=0x92000000\0" \
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BOOTENV_DESIGN_OVERLAYS \
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BOOTENV \
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--
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BOOTENV_DESIGN_OVERLAYS \
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BOOTENV \
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--
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2.39.2
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@ -1,51 +0,0 @@
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From 8afd811876b1ce8d6da6d5c804452a2b15805f5a Mon Sep 17 00:00:00 2001
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From: Ganga Ram <Ganga.Ram@tii.ae>
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Date: Wed, 5 Jul 2023 11:32:44 +0400
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Subject: [PATCH] From: Ganga Ram <Ganga.Ram@tii.ae> Date: Wed, 05 July 2023
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06:15:22 +0400 Subject: [PATCH] Riscv-Fix-build-against-binutils-2.38
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The following description is copied from the equivalent patch for the
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Linux Kernel proposed by Aurelien Jarno:
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From version 2.38, binutils default to ISA spec version 20191213. This
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means that the csr read/write (csrr*/csrw*) instructions and fence.i
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instruction has separated from the `I` extension, become two standalone
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extensions: Zicsr and Zifencei. As the kernel uses those instruction,
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this causes the following build failure:
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arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i', extension `zifencei' required
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arch/riscv/cpu/cpu.c:94: Error: unrecognized opcode `csrs sstatus,a5', extension `zicsr' required
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arch/riscv/cpu/cpu.c:95: Error: unrecognized opcode `csrw 0x003,0', extension `zicsr' required
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More detail: https://patchwork.ozlabs.org/series/283391/mbox/
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Signed-off-by: Ganga Ram <Ganga.Ram@tii.ae>
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---
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arch/riscv/Makefile | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
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diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
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index 0b80eb8d86..53d1194ffb 100644
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--- a/arch/riscv/Makefile
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+++ b/arch/riscv/Makefile
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@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
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CMODEL = medany
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endif
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-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
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+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
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+
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+# Newer binutils versions default to ISA spec version 20191213 which moves some
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+# instructions from the I extension to the Zicsr and Zifencei extensions.
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+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
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+ifeq ($(toolchain-need-zicsr-zifencei),y)
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+ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
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+endif
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+
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+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
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-mcmodel=$(CMODEL)
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PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
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--
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2.39.2
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@ -8,14 +8,14 @@ with pkgs; let
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in
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buildUBoot rec {
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pname = "uboot";
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version = "linux4microchip+fpga-2023.06";
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version = "linux4microchip+fpga-2023.09";
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src = fetchFromGitHub {
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owner = "polarfire-soc";
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repo = "u-boot";
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# from mpfs-uboot-2022.01 branch
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rev = "7e19f9dff788025403ac6a34d9acf8736eef32ff";
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sha256 = "sha256-1qmifjjNxPOUWRgZdQk6Ld5KGQk/PypSRK/ILPSsTLs";
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rev = "8f5e331e3f09cdf469d528905f5d6a7139016634";
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sha256 = "sha256-UElnkRgzcvTjAo5X9N8c1fCTrTxdpAGkntcpQlqgDy8=";
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};
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extraMakeFlags = [
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@ -24,7 +24,6 @@ buildUBoot rec {
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patches = [
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./patches/0001-Boot-environment-for-Microchip-Iciclle-Kit.patch
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./patches/0002-Riscv-Fix-build-against-binutils-2.38.patch
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];
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defconfig = "${targetBoard}_defconfig";
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enableParallelBuilding = true;
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